2016.1 Release: Heart Surgery for FuseSoC and Open SoC Debug

It’s OpTiMSoC release time! After a bit over half a year of work, we’re proud to announce our first release in this year, 2016.1. It comes with many great new features, but two are especially noteworthy: our switch to FuseSoC and the integration of Open SoC Debug. Both new features strengthen our collaborations with other projects – because sharing is caring!

Part 1: FuseSoC

Traditionally, every digital hardware project had its own build system and its own way of managing dependencies, and OpTiMSoC was no exception. Especially for people coming from the software world with all the nice package managers and module repositories specialized to the various programming languages, this seems a bit arcane. Fortunately, our friend Olof Kindgren has put a lot of work into FuseSoC, a tool that fills exactly that gap: a package manager, dependency solver and build system for digital hardware designs.

For this release, we took the chance to perform a bit of heart surgery: rip out our existing build infrastructure based on TCL files, and replace it with FuseSoC’s core description files.

While we restored all the existing functionality, i.e. to run Verilator, Vivado Synthesis and the various simulation tools through FuseSoC, we discovered a couple of issues with FuseSoC that are not all fixed upstream yet. While we work on getting all our changes upstream, we ship OpTiMSoC with a slightly modified FuseSoC version, which is available by calling optimsoc-fusesoc. One main reason is that we are using the new <vendor>:<library>:<name>:<version> (vlnv) naming scheme that we prototyped before it is now also getting into upstream. Beside that, we added Vivado and better xsim support, that we will also get into the official fusesoc version soon.

So what does that mean for you? Synthesizing a 2x2 tiled multi-core system with four compute tiles using Xilinx Vivado is now as simple as

optimsoc-fusesoc --cores-root $OPTIMSOC_SOURCE/examples build optimsoc:examples:system_2x2_cccc_nexys4ddr

Building and running a Verilator-based simulation of a single compute tile with two mor1kx cores is not much harder:

optimsoc-fusesoc --cores-root $OPTIMSOC_SOURCE/examples sim optimsoc:examples:compute_tile_sim --NUM_CORES 2

See the documentation for more examples.

Part 1b: Sharing Hardware Modules

By switching to FuseSoC, we are now able to much easier share hardware modules with other projects. In the old days, sharing meant copying HDL files around, and missing updates whenever there were new releases. With FuseSoC, it’s easy to simply point to a Git repository containing HDL files, or even download a ZIP file with HDL files from a web site (a great usage example of FuseSoC!).

We use this feature to factor out and share some of our modules.

• We share our board support packages, like the one for the Nexys 4 DDR board, with others. You can find them here.

• We also include the HDL files for GLIP (our host communication library) and Open Soc Debug (more about that below) from their upstream sources.

Right now, we ship all these sources inside our source tree to make changes and editing easier. If the rate of changes decreases over time, we can move to directly including these dependencies from upstream.

Part 2: Open SoC Debug (OSD)

OpTiMSoC has always included a rather sophisticated trace-based debug infrastructure. As it turns out, we’re not the only open source digital hardware project that needs such a infrastructure. In order to share effort, we founded, together with the LowRISC project and in close cooperation with the PULPino project, Open SoC Debug (OSD).

The goal of this project is to collaborate on debug and diagnosis components, as they are included in OpTiMSoC: components for instruction traces, system traces, memory initialization, and much more.

In this OpTiMSoC release, we see the first results of this collaboration. Our debug infrastructure is now based on OSD. All debug features that were available previously are still there, and some features are new:

• System Traces (using printf() inside the SoC software, or the OPTISMOC_TRACE macro)
• Function traces
• Reading and writing of memories in the system (now with an additional memory test and verify feature)
• Now you can also write ELF files directly into the memory, without using objdump to convert them first.
• Not really a OSD feature, but we still profit from it by using GLIP: You can now use 12 MBaud/s UART to connect to the debug system, in addition to JTAG or USB (depending on the board)

The main visible difference today are new tools to communicate with the OpTiMSoC system. Instead of our own tools like optimsoc-cli, we now use the OSD tools, like osd-cli. You find much more about how to use them in the updated tutorials in the User Guide.

Part 3: FPGA Synthesis

Support for FPGA synthesis and prebuilt example FPGA bitstreams are available again. We currently focus on the Nexys 4 DDR and the KC705 boards. But as we have defined a good board abstraction layer now, it is a lot easier to support other boards. Please get in touch with us if you want to have another board mainline supported.

Part 4: The small things

There were much more small changes throughout the system. Some things without special order.

• We now use much more SystemVerilog. That’s still a bit tricky, because every tool supports a slightly different subset of features, but in general the benefits to code readability are significant.
• Our build system has improved a lot to the point that we now can build a full release including bitstreams with one command. We use this also to do automated builds on Travis for all checkins.

The future is bright

With this release we’ve layed a lot of groundwork for even faster progress in the future. Some things are already in the pipeline, including a cool demo with live video streams.

We currently plan a project sprint and plan the next release for end of October with the following improvements:

• Re-activation of the Partitioned Global Address Space option

• Support for the KC705

• Improved Network-on-Chip configuration for better extendability

• Re-activation of the multiple clock domains support and maybe dynamic clocks

Stay tuned and join us on IRC or the mailing list.

Contributors to this release

Without the work of many individuals, a project like OpTiMSoC would be impossible. We thank everybody who contributed to this release and the projects that we included into our release.

• Nico Gutmann
• Olof Kindgren (on FuseSoC)
• Stefan Rösch
• Wei Song (on Open Soc Debug)
• Philipp Wagner
• Stefan Wallentowitz

(This list is likely to be incomplete; if you’re missing, let us know!)